1. Field of the Invention
The present invention generally relates to a data logging apparatus. More particularly, the invention is concerned with a data logging apparatus destined for use in an IC (Integrated Circuit) function test system for diagnosing IC devices as to whether or not they function satisfactorily or successfully, wherein the data resulting from the test are recorded in a memory for the purpose of subsequent analysis of fail data.
2. Description of the Prior Art
A circuit structure of an IC function test system known heretofore in the art is shown in FIG. 4 of the accompanying drawings and will be described below to make clear the subject matter contemplated by the present invention.
In this figure, reference numeral 21 denotes a pattern address counter, 22 denotes a pattern memory, 23 denotes a modulation circuit, 24 denotes a device under test, 25 denotes a driver circuit, 26A denotes a high-selector, 26B denotes a low-selector, 27 denotes a comparison circuit, 28 denotes a memory address counter and 29 denotes a timing generator.
When the device 24 is to be tested as to the function thereof, a designated patter address is placed in the pattern address counter 21. Unless any address pattern is specified, the counter 21 is set to zero. The output of the pattern address counter 21 is inputted to an addressing terminal of the pattern memory 22 which then responds thereto by outputting pattern data.
The pattern data outputted from the pattern memory 22 is processed by the modulation circuit 23, as a result of which a pattern required for testing the function of the device 24 of concern is obtained. The pattern is then applied to the device 24 under test as a corresponding electric signal through the driver circuit 25. A signal outputted from the device 24 under test in response to the application of the pattern data signal is supplied to the inputs of the high-selector 26A and the low-selector 26B, respectively. In case an expected pattern supplied from the pattern memory 22 is of high level, the result of the comparison between the expected pattern and the pattern data signal selected by the high-selector 26A is produced as an output signal of the comparison circuit 27. On the other hand, when the expected pattern is of a low level, the former is compared with the pattern data signal inputted to the low-selector 26B, the result of which is produced as the output signal of the comparison circuit 27. In any case, the output signal of the comparison circuit 27 is supplied to a data logging apparatus 100.
The pattern address counter 21 then places therein a next address under the timing of a basic clock signal T.sub.0 which is produced by the timing generator 29. On the other hand, the memory address counter 28 starts the address counting operation only when the pattern address has reached a data logging start address which has previously been set up as the condition for the data logging before starting the function test. It should however be mentioned that the memory address counter 28 is incremented approximately under the timing of the basic clock T.sub.0.
The data logging apparatus 100 mentioned above is destined to serve as a circuit for writing in a data logging memory (not shown) the pattern addresses, the associated memory addresses and the fail data. The data logging memory also serves for storing time-serially input/output information to be furnished to a device 24 under test upon performing the function test.
Now, operation of the data logging apparatus 100 of the prior art will be elucidated by reference to a timing chart shown in FIG. 5.
In this figure, there are illustrated the basic clock signal T.sub.0 at (a), data of the pattern address at (b), a strobe signal at (c), the output data of the comparison circuit 27 at (d), the fail data at (e), the memory address at (f) and a memory write signal at (g), respectively.
Under the timing of the clock signal T.sub.0 generated by the timing generator 29 and shown at (a) in FIG. 5, application of the signal to the device 24 under test is controlled. At this juncture, a period of the basic timing signal T.sub.0 is referred to as a rate.
The pattern address data shown at (b) in FIG. 5 is generated under the timing of the basic clock T.sub.0 as well.
The strobe signal shown in FIG. 5 at (c) serves as a timing control signal for controlling the timing of fetching the output of the comparison circuit 27 as a signal representing the result of the test. This strobe signal (c) is outputted by a strobe circuit 110 shown in FIG. 4 at time intervals previously set with reference to the basic clock T.sub.0. More specifically, the strobe signal shown at (c) in FIG. 5 may be so set as to fall within a first rate (period) from the rising-up of the basic clock T.sub.0, as indicated by T.sub.1 or fall within a succeeding rate (period), as indicated by T.sub.2 or fall within a n-th rate in more general terms. The numerals shown above the strobe pulses, respectively, indicate the strobe signal identification numbers, respectively, wherein those strobe pulses affixed with the same numeral are produced at the same time interval.
The output data (d) of the comparison circuit 27 represent the results of the comparisons between the output data actually outputted from the device 24 under test and the expected data to be outputted.
Shown at (e) in FIG. 5 are fail data latched from the output (d) of the comparison circuit 27 in response to the strobe signal (c) of FIG. 5.
Shown at (f) in FIG. 5 is the memory address signal which is in synchronism with the basic clock T.sub.0.
Shown at (g) in FIG. 5 is the memory write pulse signal derived by delaying the strobe signal (c) for a predetermined amount.
Assuming now that the pattern addresses N1, N2, N3 and so forth, the fail data A, B, C and so forth and the addresses A1, A2, A3 and so forth are written in the data logging memory, the state of the data written in this memory may be such as shown in FIG. 6. Referring to this figure, although the pattern address data N2 should have been written at the memory address A2, the pattern address data N3 has actually been written at this memory address, which can be explained by the fact that the strobe signal (c) for the pattern address (b) becomes different for the pattern data N2, as can be seen in FIG. 5. More specifically, the strobe signal for the pattern address N2 shown at (b) in FIG. 5 is set to extend into the rate (period) of the pattern address N3 beyond the rate of the pattern address data N2. As a consequence, at the time point when the fail data B shown at (e) in FIG. 5 makes appearance, the pattern address N2 shown at (b) in FIG. 5 has already been replaced by the pattern address N3, whereby the pattern address N3 is erroneously written in the data logging memory at the address A2, as illustrated in FIG. 6.
Under the circumstances, as an attempt to evade the trouble mentioned above, the pattern addresses generated in response to the strobe pulses at different time intervals have heretofore been once latched at timings each corresponding to a half of the time interval of the relevant strobe pulse, whereon the other half of the strobe pulse duration is utilized for realizing the writing of the pattern address and the fail data.
FIG. 7 of the accompanying drawings shows a structure of the data logging apparatus which is so arranged as to latch the data at time intervals corresponding to halves of the strobe pulses, respectively.
In FIG. 7, reference numeral 31 denotes a selector, 32 denotes a flip-flop (FF for short), 33 denotes a write pulse generating circuit, 34 denotes a fail data storing memory, 35 denotes a memory address data latch circuit, 36 denotes a pattern address data latch circuit and 37 denotes a pattern address storing memory.
The memory address data latch circuit 35 is constituted by a selector 35A, another selector 35C, a flip-flop 35B and another flip-flop 35D. Similarly, the pattern address data latch circuit 36 is composed of selectors 36A and 36C and flip-flops (FF) 36B and 36D.
Operation of the data logging apparatus shown in FIG. 7 will be described by reference to a timing chart of FIG. 8.
Shown at (e) in FIG. 8 is the pattern address data latched by the flip-flop (FF) 36B at a timing corresponding to a half of the time interval T.sub.1 of the strobe pulse STD1 selected in response to the strobe select signal by the selector 36A constituting a part of the pattern address data latch circuit 36 shown in FIG. 7, while the pattern address data 2 shown at (f) in FIG. 8 is latched by the flip-flop (FF) 36D in response to the strobe signal STB1 selected by the strobe signal selector 36C of the pattern address latch circuit 36 shown in FIG. 7.
The fail data shown at (g) in FIG. 8 is obtained by latching the output (FIG. 8, d) of the comparison circuit (27 in FIG. 4) in response to the strobe signal STB1 selected by the selector 31 shown in FIG. 7. The memory addresses are also outputted under the timing of the strobe signal STB1 as in the case of the pattern addresses.
In this manner, in the case of the pattern address data 2 shown at (f) in FIG. 8 which is outputted under the timing of the strobe signal 1 shown at (c) in FIG. 8, the pattern address data and the fail data shown at (g) in FIG. 8 are written in the pattern address memory 37 and the fail data memory 34, respectively, in response to the memory write signal derived from the strobe signal, as shown at (i) in FIG. 8, by the write pulse generating circuit 33 shown in FIG. 7.
At that time, the pattern addresses at which the fail data are written correspond to N1, N4, N5 and N6, respectively, because the strobe signal selected by the selectors 31, 35C and 36C is the strobe signal 1 shown at (c) in FIG. 8, and no fail data are written at the pattern addresses N2 and N3.
Consequently, in order to obtain the fail data for the pattern address N2, the strobe signal 2 has to be so selected as to write the fail data at the timing corresponding to a half of the time interval T.sub.2 of the strobe signal 2 to thereby execute again the test with the aid of the strobe signal 2.
The timing relations among the pattern address, the fail data, the memory address and the memory write signal at the time when the strobe signal 2 is selected are shown at (k), (l), (m) and (n), respectively, in FIG. 8.
It is thus apparent that, in general, in order to allow the time interval of the strobe signal to extend so as to fall within the n-th rate (period), it is necessary at the first latch timing to write the fail data at the time interval corresponding to 1/n.
As will be understood from the foregoing, the prior art data logging apparatus indispensably requires the selection of the appropriate strobe signal without fail upon every execution of the data logging, which means that when the data logging is to be performed for all the patterns, selection of the strobe signals of the different time intervals and execution of the test must be repeated, which of course requires a much complicated and expensive circuit configuration, not to say of a problem that a long time is taken for performing the function test of IC devices.